1. Field of the Invention
The present invention relates to a static memory cell used as a memory cell for an SRAM (static random access memory).
2. Description of the Related Art
FIG. 6 exemplifies a static memory cell used for a conventional SRAM. This static memory cell comprises a flip-flop circuit 10 formed of a first inverter circuit 1 and a second inverter circuit 2 so as to have a capacity to record data of 1 bit. In the first inverter circuit 1, a resistance 1a and an n-channel Metal Oxide Semiconductor Field Effects Transistor (MOSFET) 1b are connected in series between a power source (V.sub.cc) and the ground (GND). Similarly, in the second inverter circuit 2, a resistance 2a and an n-channel MOSFET 2b are connected in series between the V.sub.cc and the GND. A gate of the n-channel MOSFET 1b functions as an input of the first inverter circuit 1, and a first connector node 3 between the resistance 1a and the n-channel MOSFET 2b functions as an output of the first inverter circuit 1. A gate of the n-channel MOSFET 2b functions as an input of the second inverter circuit 2, and a second connector node 4 between the resistance 2a and the n-channel MOSFET 1b functions as an output of the second inverter circuit 2. The output of the first inverter circuit 1 is connected to the input of the second inverter circuit 2 through the first connector node 3. The output of the second inverter circuit 2 is connected to the input of the first inverter circuit 1 through the second connector node 4. In the flip-flop circuit 10 consisting of the inverter circuits 1 and 2, when the voltage level of the first connector node 3 is high, the n-channel MOSFET 2b of the second inverter circuit 2 is in an ON-state, so that the voltage level of the second connector node 4 is stabilized low. Similarly, when the voltage level of the second connector node 4 is high, the n-channel MOSFET 1b of the first inverter circuit 1 is in the ON-state, so that the voltage level of the first connector node 3 is stabilized low.
The connector node 3 is connected to a first bit line B through a transfer gate 5. The connector node 4 is connected to a second bit line B through a transfer gate 6. The transfer gates 5 and 6 are each consisted of an n-channel MOSFET and connected to the same word line WL. Thus, they are each controlled so as to be turned to the ON-state or OFF-state simultaneously. The voltage levels of the bit lines B and B are set to be high and low, complementally.
In the case where data is written on the above-mentioned static memory cell, the voltage levels of the bit lines B and B are set to be high and low, or to be low and high respectively, and then the voltage level of the word line WL is turned to be high. Now assuming that the voltage level of the first bit line B is set to be high and that of the second bit line B is set to be low, the two transfer gates 5 and 6 are turned to the ON-state when the voltage level of the word line WL is turned to be high. As a result, the voltage level of the first connector node 3 becomes high and that of the second connector node 4 becomes low. Even after the voltage level of the word line WL is turned back to be low and the two transfer gates 5 and 6 are turned to the OFF-state, the voltage level of the first connector node 3 is maintained at high, and that of the second connector node 4 is maintained at low, thereby realizing data writing.
In the case where the data is read from the static memory cell, the voltage levels of the bit lines B and B are made so as to have the same voltage, and then the voltage level of the word line WL is turned to be high. Now assuming that the voltage level of the first connector node 3 is maintained at high as described above, the voltage level of the word line WL is turned to be high, so that the two transfer gates 5 and 6 are turned to the ON-state. Thus, the voltage of the first bit line B is increased due to the voltage level (high level) of the first connector node 3, and the voltage of the second bit line B is decreased due to the voltage level (low level) of the second connector node 4. The potential difference between the increased potential of the first bit line B and the decreased potential of the second bit line B is amplified by a differential amplifier (not shown), thereby realizing data reading.
However, the above-mentioned conventional static memory cell has a disadvantage in that the inverter circuits I and 2 are not positively operated when the voltage of the V.sub.cc is low.
For example, in the case where the voltage level of the first connector node 3 is low and that of the second connector node 4 is high, the voltage levels of the bit lines B and B are set to be high and low, respectively at the time of t.sub.11, and then the voltage level of the word line WL is turned so as to be high. In this case, the voltage of the first connector node 3 is gradually increased, while the voltage of the second connector node 4 is decreased to the voltage level of the GND as shown in FIG. 7. Herein, the n-channel MOSFET 1b of the first inverter circuit 1 is turned to the OFF-state due to a decrease of the voltage of the second connector node 4. On the other hand, the n-channel MOSFET 2b of the second inverter circuit 2 is turned to the ON-state due to a sufficient increase of the voltage of the first connector node 3. Thus, data is positively written on and stored in the memory cell.
However, as shown in FIG. 7, in the case where the voltage of the V.sub.cc is low, so that the voltage of the first connector node 3 is not increased up to the threshold voltage V.sub.th, the n-channel MOSFET 2b of the second inverter circuit 2 is not positively turned to the ON-state. Accordingly, when the voltage level of the word line WL is turned to be low at the time of t.sub.12, and the two transfer gates 5 and 6 are turned back to be in the OFF-state, the voltage of the second connector node 4 is increased to some extent from the voltage level of the GND, and thus the potential difference V.sub.d between the connector nodes 3 and 4 still remain insufficient. When the data is read under this situation, the potential difference between the bit lines B and B is so insufficient that the differential amplifier cannot be operated normally.
As is apparent from the above, in the case where the voltage of the V.sub.cc is low, the n-channel MOSFETs 1b and 2b may not be operated normally, and thus data cannot be read from the static memory cell.